1. Field of the Invention
The present invention is directed to a method for manufacturing and related structure of thin film transistors ("TFT"s) for use in an active matrix liquid crystal display ("AMLCD"s).
2. Description of the Related Art
AMLCDs include switching devices, such as integrated TFT active elements for driving and/or controlling each pixel.
As shown in FIG. 1A, in a conventional LCD having an integrated TFT array, substantially rectangular pixel electrodes 47 are closely arranged in rows and columns on a transparent glass substrate. Each of a plurality of gate bus lines (address lines) 13 is provided between respective rows of the pixel electrodes 47, and each of a plurality of source bus lines (data lines) 14 is provided between columns of pixel electrodes 47.
FIG. 1B illustrates an enlarged plan view of an individual pixel of the LCD. The pixel includes a TFT having a gate electrode 33, protruding from a gate bus line 13, formed on a transparent glass substrate. An insulating layer covers the gate electrode, upon which source bus lines 14 are oriented perpendicular to the gate bus lines. A semiconductor layer is formed on the insulating layer covering the gate bus line and the gate electrode adjacent respective intersections of the gate bus lines 13 and the source bus lines 14. Opposing source and drain electrodes are provided on each semiconductor layer, thereby completing the TFT active elements.
A process for manufacturing a conventional LCD is described below with reference to FIGS. 2A to 2E, which show cross-sectional views taken along a line 2--2 of FIG. 1B during the manufacturing process.
A gate electrode 33 is first formed on a transparent glass substrate 31 by depositing and patterning a first metal layer (FIG. 2A). A first insulating layer (gate insulating layer) 35 made of SiNx, an a-Si semiconductor layer 37 and a second SiNx insulating layer are then successively deposited on the entire surface of the substrate. An etch-stopper 40 is next formed by patterning the second insulating layer (FIG. 2B), followed by deposition of an n.sup.+ a-Si impurity doped semiconductor layer 39 on the entire surface of the substrate. Semiconductor layer 37 is then patterned together with the n+semiconductor layer 39 (FIG. 2C).
Next, a second metal layer 43 is sputtered on the entire surface of the substrate and source and drain electrodes 43a and 43b are formed by patterning the second metal layer. The portion of the n.sup.+ semiconductor layer 39 which is not covered by the source and drain electrodes is then etched by using the source and drain electrodes as a mask (FIG. 2D).
After forming the source and drain electrodes, insulating passivation layer 45 is formed by depositing a silicon nitride layer on the substrate, and a contact hole is formed in the insulating passivation layer overlying the drain electrode. An ITO layer is sputtered on the substrate surface and a pixel electrode 47 is formed by patterning the ITO layer, such that the pixel electrode 47 electrically contacts the drain electrode 43b (see FIG. 2E).
The TFT manufactured by the conventional method described above is known as an etch-stop type. Preferably, the portion of the semiconductor layer 39 not covered by the source and drain electrodes should be completely etched. Accordingly, the etching should continue for a considerable time. Thus, the etch-stop 40 is included to prevent the semiconductor layer 37 from being over-etched. However, including the etch stop adds an additional mask step, which can reduce yield. In particular, this additional step is complicated and requires specific exposure times and temperatures, as well as photoresist development and baking. If these parameters are not precisely controlled, yield can suffer. Therefore, the number of mask steps should preferably be reduced.